"One of the most significant developments in the area of design verification over the last decade is the development of algorithmic methods for verifying temporal specification of finite-state designs. A frequent criticism against this approach, however, is that verification is done after significant resources have already been invested in the development of the design. Since designs invariably contains errors, verification simply becomes part of the debugging process. The critics argue that the desired goal is to use the specification in the design development process in order to guarantee the development of correct designs. This is called design synthesis. In this talk I will review 50 years of research on the synthesis problem, describe the automata-theoretic approach developed to solve this problem, and address current challenges."